Sinopsis
Preface; Gyungho Lee, Pen-Chung Yew. 1. EquiMax Optimal Scheduling Formulation; S.-A.-A. Touati. 2. An Efficient Semi-Hierarchical Array Layout; N.P. Drakenberg, et al. 3. Impact of Tile-Size Selection for Skewed Tiling; Yonghong Song, Zhiyuan Li. 4. Improving Software Pipelining by Hiding Memory Latency; M. Bedy, et al. 5. Register Allocation for Embedded System; Heung-Bok Lee, et al. 6. Is Compiling for Performance == Compiling for Power?; M. Valluri, L.K. John. 7. A Technology-Scalable Architecture for Fast Clocks and High ILP; K. Sankaralingam, et al. Topic Index. Author Index.
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