Analog Circuit Design: High-Speed Analog-to-Digital Converters, Mixed Signal Design; PLLs and Synthesizers - Tapa blanda

Sinopsis

Preface. Part I: High-Speed Analog-to-Digital Converters. Introduction. Speed-Power-Accuracy Trade-off in high-speed Analog-to-digital converters: Now in the future...; M. Steyaert, K. Uyttenhove. A dual model 700 Msamples/s 6-bit, 200 Msamples/s 7-bit A/D converter in 0.25 micron digital CMOS; K. Nagaraj, et al. A 3.3 V 12b 50-Ms/s A/D converter in 0.6 micron CMOS with over 80-dB SFDR; H. Pan, et al. A 10-bit 20-30 MSPS CMOS subranging ADC with 9.5 Effective bits at Nyquist; B. Brandt, J. Lutsky. A 2.5 MHz output-rate delta-sigma ADC with 90dB SNR and 102dB SFDR; I. Fujimori, et al. A 13-bit bandpass sigma-delta modulator for 10.7 MHz digital IF with a MHz sampling rate; J. van Engelen. Part II: Mixed Signal Design. Introduction. System-level design issues for mixed-signal ICs and telecom frontends; G. Gielen. Mixed signal: Design issues; H. Casier. Top-down design of mixed-signal circuits; K. Kundert. Computer aided design for integrated systems; F.M. Stubbe. Mixed mode sigma-delta ADC design for high-quality audio; G. Cesura, et al. Mixed mode telecom design; D.M.W. Leenaerts, P.W.H. de Vreede. Part III: PLLs and Synthesizers. Introduction. On placing multiple inductor-based VCOs on the same mixed-signal substrate; J. Parker, M. Altmann. Fully integrated CMOS frequency synthesizers for wireless communications; B. De Muer, M. Steyaert. Design and optimization of RFCMOS-circuits for integrated PLL's and synthesizers; M. Tiebout. Frequency synthesis for integrated transceivers; J.-W. Eikenbroek, S. Mattison. PLL frequency synthesizers: Phase noise issues and wide-band loops; M. de Queiroz Tavares. Low-power circuits for RF-frequency synthesizers in the low GHz range; D. Pfaff, Q. Huang.

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