This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.
"Sinopsis" puede pertenecer a otra edición de este libro.
Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.
Sridhar Gangadharan is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.
· Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints;
· Includes key topics of interest to a synthesis, static timing analysis or place and route engineer;
· Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing;
· Explains fundamental concepts and provides exact command syntax.
"Sobre este título" puede pertenecer a otra edición de este libro.
GRATIS gastos de envío desde Alemania a España
Destinos, gastos y plazos de envíoEUR 4,76 gastos de envío desde Reino Unido a España
Destinos, gastos y plazos de envíoLibrería: Buchpark, Trebbin, Alemania
Condición: Sehr gut. Zustand: Sehr gut | Seiten: 256 | Sprache: Englisch | Produktart: Bücher. Nº de ref. del artículo: 23271956/2
Cantidad disponible: 1 disponibles
Librería: Better World Books: West, Reno, NV, Estados Unidos de America
Condición: Very Good. Former library book; may include library markings. Used book that is in excellent condition. May show signs of wear or have minor defects. Nº de ref. del artículo: 50108526-75
Cantidad disponible: 1 disponibles
Librería: SecondSale, Montgomery, IL, Estados Unidos de America
Condición: Good. Item in good condition. Textbooks may not include supplemental items i.e. CDs, access codes etc. Nº de ref. del artículo: 00081528679
Cantidad disponible: 1 disponibles
Librería: Goodwill, Brooklyn Park, MN, Estados Unidos de America
Condición: VeryGood. Nº de ref. del artículo: 2Y6U1A000V1Y_ns
Cantidad disponible: 1 disponibles
Librería: Ria Christie Collections, Uxbridge, Reino Unido
Condición: New. In English. Nº de ref. del artículo: ria9781461432685_new
Cantidad disponible: Más de 20 disponibles
Librería: moluna, Greven, Alemania
Gebunden. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides a hands-on guide to create constraints for synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints Explains fundamental concepts around SDC constraints and its applica. Nº de ref. del artículo: 4198073
Cantidad disponible: Más de 20 disponibles
Librería: Goodwill of Silicon Valley, SAN JOSE, CA, Estados Unidos de America
Condición: acceptable. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Acceptable condition! Any other included accessories are also in Acceptable condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear such as cover tears discoloration, staining, marks, scuffs, etc. All pages intact. Nº de ref. del artículo: GWSVV.1461432685.A
Cantidad disponible: 1 disponibles
Librería: GreatBookPricesUK, Woodford Green, Reino Unido
Condición: New. Nº de ref. del artículo: 19358735-n
Cantidad disponible: Más de 20 disponibles
Librería: Brook Bookstore On Demand, Napoli, NA, Italia
Condición: new. Questo è un articolo print on demand. Nº de ref. del artículo: f19822970c5e66ae3483d78d1611d19c
Cantidad disponible: Más de 20 disponibles
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. 256 pp. Englisch. Nº de ref. del artículo: 9781461432685
Cantidad disponible: 2 disponibles