Artículos relacionados a Hardware Component Modeling: 5 (Current Issues in Electronic...

Hardware Component Modeling: 5 (Current Issues in Electronic Modeling) - Tapa blanda

 
9781461285793: Hardware Component Modeling: 5 (Current Issues in Electronic Modeling)
Tapa blanda
ISBN 10: 1461285798 ISBN 13: 9781461285793
Editorial: Springer, 2011

Sinopsis

The VITAL specification addresses the issues of interoperability, backannotation and high performance simulation for sign-off quality ASIC libraries in VHDL. VITAL provides modeling guidelines and a set of pre-defined packages (containing pre-defined routines for modeling functionality and timing) to facilitate the acceleration of designs which use cells from a VITAL library. The VITAL Level-I guidelines constrain the modeling capabilities provided by VHDL in order to facilitate higher performance (Figure I). Accumulating "gains" Constrained "flexibility" Higher performance & Increased capacity Benefits Flexibility FujI VHDL 1076 Figure 1: VHDL and VITAL Even within the Level-I guidelines, there are several ways in which a model can be written. In this chapter, we highlight the various modeling trade-offs and provide guidelines which can be used for developing efficient models. We will also discuss the techniques that can be used by tool developers to accelerate the simulation of VIT AL­ based designs. 2.2. OVERVIEW OF A VITAL LEVEL-l ARCIDTECTURE The VITAL specification is versatile enough to support several modeling styles e.g., distributed delay style, pin-to-pin delay style etc. In general, a VITAL Level-I model can have the structure illustrated in Figure 2.

"Sinopsis" puede pertenecer a otra edición de este libro.

De la contraportada

The VITAL specification addresses the issues of interoperability, backannotation and high performance simulation for sign-off quality ASIC libraries in VHDL. VITAL provides modeling guidelines and a set of pre-defined packages (containing pre-defined routines for modeling functionality and timing) to facilitate the acceleration of designs which use cells from a VITAL library. The VITAL Level-I guidelines constrain the modeling capabilities provided by VHDL in order to facilitate higher performance (Figure I). Accumulating "gains" Constrained "flexibility" Higher performance & Increased capacity Benefits Flexibility FujI VHDL 1076 Figure 1: VHDL and VITAL Even within the Level-I guidelines, there are several ways in which a model can be written. In this chapter, we highlight the various modeling trade-offs and provide guidelines which can be used for developing efficient models. We will also discuss the techniques that can be used by tool developers to accelerate the simulation of VIT AL­ based designs. 2.2. OVERVIEW OF A VITAL LEVEL-l ARCIDTECTURE The VITAL specification is versatile enough to support several modeling styles e.g., distributed delay style, pin-to-pin delay style etc. In general, a VITAL Level-I model can have the structure illustrated in Figure 2.

"Sobre este título" puede pertenecer a otra edición de este libro.

Editorial
Springer
Año de publicación
2011
Idioma
Inglés
ISBN 10 
1461285798
ISBN 13 
9781461285793
Encuadernación
Tapa blanda
Número de páginas
134
Editor
Bergé Jean-Michel, Levia Oz, Rouillard Jacques
Contacto del fabricante
Springer Nature Customer Service Center GmbH
ProductSafety@springernature.com

Europaplatz 3
Heidelberg
69115
Alemania