High-Level Verification: Methods and Tools for Verification of System-Level Designs - Tapa dura

Acerca del autor

Charlotte y Peter Fiell son dos autoridades en historia, teoría y crítica del diseño y han escrito más de sesenta libros sobre la materia, muchos de los cuales se han convertido en éxitos de ventas. También han impartido conferencias y cursos como profesores invitados, han comisariado exposiciones y asesorado a fabricantes, museos, salas de subastas y grandes coleccionistas privados de todo el mundo. Los Fiell han escrito numerosos libros para TASCHEN, entre los que se incluyen 1000 Chairs, Diseño del siglo XX, El diseño industrial de la A a la Z, Scandinavian Design y Diseño del siglo XXI.

De la contraportada

This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence the topic area is also referred to as system level verification. Since such descriptions can also capture software, especially device drivers or other embedded software, this book will be of interest to both hardware and software designers.
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The methodology presented in this book relies upon advances in synthesis techniques, as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically.

The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.

• Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification;

• Uses a combination of formal techniques to do scalable verification of system designs completely automatically;

• Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-level RTL;

• Written by researchers working in mainstream hardware and software design and includes results from both academia and industry