Compilers and Operating Systems for Low Power - Tapa blanda

Sinopsis

List of Figures. List of Tables. Contributing Authors. Preface. 1: Low Power Operating System for Heterogeneous Wireless Communication System; Suet-Fei Li, R. Sutton, J. Rabaey. 1. Introduction. 2. Event-driven versus General-purpose OS. 3. Low Power Reactive OS for Heterogeneous Architectures. 4. Conclusion and Future Work. References. 2: A Modified Dual-Priority Scheduling Algorithm for Hard Real-Time Systems to Improve Energy Savings; M.A. Moncusí, A. Arenas, J. Labarta. 1. Introduction. 2. Dual-Priority Scheduling. 3. Power-Low Modified Dual-Priority Scheduling. 4. Experimental Results. 5. Summary. References. 3: Toward the Placement of Power Management Points in Real-Time Applications; N. AbouGhazaleh, D. Mossé, B. Childers, R. Melhem. 1. Introduction. 2. Model. 3. Sources of Overhead. 4. Speed Adjustment Schemes. 5. Optimal Number of PMPs. 6. Conclusion. Appendix: Derivation of Formulas. References. 4: Energy Characterization of Embedded Real-Time Operating Systems; A. Acquaviva, L. Benini, B. Riccó. 1. Introduction. 2. Related Work. 3. System Overview. 4. Characterization Strategy. 5. RTOS Characterization Results. 6. Summary of Findings. 7. Conclusions. References. 5: Dynamic Cluster Reconfiguration for Power and Performance; E. Pinheiro, R. Bianchini, E.V. Carrera, T. Heath. 1.Motivation. 2. Cluster Configuration and Load Distribution. 3. Methodology. 4. Experimental Results. 5. Related Work. 6. Conclusions. References. 6: Energy Management of Virtual Memory on Diskless Devices; J. Hom, U. Kremer. 1. Introduction. 2. Related Work. 3. Problem Formulation. 4. EELRM Prototype Compiler. 5. Experiments. 6. Future Work. 7. Conclusion. References. 7: Propagating Constants Past Software to Hardware Peripherals on Fixed-Application Embedded Systems; G. Stitt, F. Vahid. 1. Introduction. 2. Example. 3. Parameters in Cores. 4. Propagating Constants from Software to Hardware. 5. Experiments. 6. Future Work. 7. Conclusions. References. 8: Constructive Timing Violation for Improving Energy Efficiency; T. Sato, I. Arita. 1. Introduction. 2. Low Power via Fault-Tolerance. 3. Evaluation Methodology. 4. Simulation Results. 5. Related Work. 6. Conclusion and Future Work. References. 9: Power Modeling and Reduction of VLIW Processors; Weiping Liao, Lei He. 1. Introduction. 2. Cycle-Accurate VLIW Power Simulation. 3. Clock Ramping. 4. Experimental Results. 5. Conclusions and Discussion. References. 10: Low-Power Design of Turbo Decoder with Exploration of Energy-Throughput Trade-off; A. Vandecappelle, B. Bougard,

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