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9781441951496: Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power

Sinopsis

The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ­ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif­ ferent conversion techniques applicable in this range of sample rates is dis­ cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi­ zation of capacitor sizes, design of low-voltage transmission gates, and opti­ mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech­ niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.

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Reseña del editor

The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ­ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif­ ferent conversion techniques applicable in this range of sample rates is dis­ cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi­ zation of capacitor sizes, design of low-voltage transmission gates, and opti­ mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech­ niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.

Reseña del editor

This volume of Analog Circuit Design concentrates on three topics: Low-Power Low-Voltage Design; Integrated Filters, and Smart Power. The book comprises six papers on each topic written by internationally recognised experts. These papers have a tutorial nature aimed at improving the design of analog circuits. The book is divided into three parts:

  • Part I, Low-Power Low-Voltage Design, describes the latest techniques for producing analog circuits with low-voltage low-power requirements. These circuits have an important role to play in the increasing trend towards portable products, where battery life is an important design factor. The papers cover design techniques for amplifiers, analog-to-digital converters, micro-power analog filters and medical devices.
  • Part II, Integrated Filters, presents papers which detail nearly all known techniques to construct integrated filters. These filters all use resistors and capacitors to obtain the filtering function due to the low quality of inductors in silicon. Integration of the filtering function on chips is important to reduce system cost and provide greater accuracy.
  • Part III, Smart Power, illustrates up-to-date techniques for implementing thermal detectors and protection networks to improve reliability and the lifetime of many analog devices. These devices are more specifically those with different analog blocks operating at different temperatures. Smart Power is thus never limited to circuit design only, but must also include packaging and cooling considerations; it is system design.
Analog Circuit Design is an essential reference source for analog design engineers wishing to keep abreast with the latest developments in the field. The tutorial nature of the contributions also makes the book suitable for use in an advanced course.

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Plassche, Rudy J. van de|Sansen, Willy M.C.|Huijsing, Johan
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Rudy J. Van De Plassche
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized. 412 pp. Englisch. Nº de ref. del artículo: 9781441951496

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Rudy J. Van De Plassche
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Taschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized. Nº de ref. del artículo: 9781441951496

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Rudy J. Van De Plassche
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ISBN 10: 1441951490 ISBN 13: 9781441951496
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Taschenbuch. Condición: Neu. Neuware -The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 412 pp. Englisch. Nº de ref. del artículo: 9781441951496

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Plassche, Rudy J. van de (Editor) / Sansen, Willy M.C. (Editor) / Huijsing, Johan (Editor)
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