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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test: 40 (Frontiers in Electronic Testing) - Tapa dura
Sinopsis
The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.
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Acerca del autor
Prof. Sachdev has authored several successful books with Springer
De la contraportada
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.
Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired.
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
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CMOS Sram Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware Sram Design and Test
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SPRINGER NATURE, 2008
ISBN 10: 1402083629
ISBN 13: 9781402083624
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Librería: Buchpark, Trebbin, Alemania
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CMOS Sram Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware Sram Design and Test
Publicado por
SPRINGER NATURE, 2008
ISBN 10: 1402083629
ISBN 13: 9781402083624
Antiguo o usado
Tapa dura
Librería: Buchpark, Trebbin, Alemania
Calificación del vendedor: 5 de 5 estrellas
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Frontiers in Electronic Testing, 40)
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Frontiers in Electronic Testing, 40)
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
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Gebunden. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Gives a process-aware perspective on SRAM circuit design and testProvides detailed coverage of SRAM cell stability, stability sensitivity and analytical evaluation of Static Noise MarginIntroduces the concept of stability fault modelling. Nº de ref. del artículo: 4095486
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Frontiers in Electronic Testing, 40)
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Hardcover)
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Springer-Verlag New York Inc., New York, NY, 2008
ISBN 10: 1402083629
ISBN 13: 9781402083624
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Calificación del vendedor: 5 de 5 estrellas
Hardcover. Condición: new. Hardcover. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Nº de ref. del artículo: 9781402083624
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Frontiers in Electronic Testing, 40)
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Condición: New. Nº de ref. del artículo: ABLIING23Mar2411530145191
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CMOS Sram Circuit Design and Parametric Test in Nano-Scaled Technologies : Process-Aware Sram Design and Test
Librería: AHA-BUCH GmbH, Einbeck, Alemania
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Buch. Condición: Neu. Neuware - CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies. Nº de ref. del artículo: 9781402083624
Cantidad disponible: 2 disponibles
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Hardcover)
Publicado por
Springer-Verlag New York Inc., New York, NY, 2008
ISBN 10: 1402083629
ISBN 13: 9781402083624
Nuevo
Tapa dura
Librería: AussieBookSeller, Truganina, VIC, Australia
Calificación del vendedor: 5 de 5 estrellas
Hardcover. Condición: new. Hardcover. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability. Nº de ref. del artículo: 9781402083624
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