Analysis of Cache Memories in Highly Parallel Systems (Classic Reprint) - Tapa blanda

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Excerpt from Analysis of Cache Memories in Highly Parallel Systems

Analogous to reducing the effective memory access time in uniprocessor sys tems, a memory hierarchy can be used in parallel processor systems that employ a PE to central memory connection network the hierarchy comprising a local memory associated with each PE and a large central memory. The inclusion of a local memory reduces the effective memory access time since the resulting access time is an average of the network and local memory latencies. Moreover, since the local memory services a percentage of all memory requests. Network traffic is diminished, thus reducing network latency. The indiscriminate use of a local memory, however, can introduce memory coherence violations a memory system.

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