A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.
"Sinopsis" puede pertenecer a otra edición de este libro.
A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.
"Sobre este título" puede pertenecer a otra edición de este libro.
Librería: Mispah books, Redhill, SURRE, Reino Unido
Paperback. Condición: Like New. Like New. book. Nº de ref. del artículo: ERICA79612889103046
Cantidad disponible: 1 disponibles