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Sinopsis
An invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield projection and enhancement, fault tolerant and testing techniques, and self-checking and coding techniques. No subject index. Annotation copyright Book News, Inc. Portland, Or.
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Reseña del editor
An invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield projection and enhancement, fault tolerant and testing techniques, and self-checking and coding techniques. No subject index. Annotation copyright Book News, Inc. Portland, Or.
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- EditorialIEEE Publications,U.S.
- Año de publicación1995
- ISBN 10 0818671076
- ISBN 13 9780818671074
- EncuadernaciónTapa dura
- IdiomaInglés
- Número de páginas305
- Contacto del fabricanteno disponible
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Imagen del vendedor
The IEEE international workshop on Defect & Fault-Tolerance in VLSI Systems, Proceedings, 1995.
Publicado por
IEEE Computer Society Press, Los Alamitos, 1995
ISBN 10: 0818671076
ISBN 13: 9780818671074
Antiguo o usado
Tapa dura
Librería: Lost and Found Books, Healesville, VIC, Australia
Calificación del vendedor: 5 de 5 estrellas
hard cover. No Jacket. Illustrated in black and white. 305 pages VG. Slight shelf wear to covers, overall very good condition. Nº de ref. del artículo: 13953
Cantidad disponible: 1 disponibles