Artículos relacionados a Reuse Methodology Manual: For System-on-a-Chip Designs
Sinopsis
Foreword. Preface to the Second Edition. Acknowledgements. 1. Introduction. 2. The System-on-a-Chip Design Process. 3. System-Level Design Issues: Rules and Tools. 4. The Macro Design Process. 5. RTL Coding Guidelines. 6. Macro Synthesis Guidelines. 7. Macro Verification Guidelines. 8. Developing Hard Macros. 9. Macro Deployment: Packaging for Reuse. 10. System Integration with Reusable Macros. 11. System-Level Verification Issues. 12. Data and Project Management. 13. Implementing a Reuse Process. Bibliography.
"Sinopsis" puede pertenecer a otra edición de este libro.
Reseña del editor
Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the vast numbers of gates now available. This work outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. It is an attempt to capture and improve on current practices in the industry, and to give a coherent, integrated view of the design process.
"Sobre este título" puede pertenecer a otra edición de este libro.
EUR 11,87
EUR 8,92 gastos de envío desde Estados Unidos de America a España
Destinos, gastos y plazos de envíoComprar nuevo
Ver este artículo
EUR 51,58
EUR 38,20 gastos de envío desde Estados Unidos de America a España
Destinos, gastos y plazos de envíoResultados de la búsqueda para Reuse Methodology Manual: For System-on-a-Chip Designs
Imagen de archivo
Reuse Methodology Manual for System-On-A-Chip Designs
Publicado por
Kluwer Academic Publishers, 1999
ISBN 10: 0792385586
ISBN 13: 9780792385585
Antiguo o usado
Tapa dura
Librería: ThriftBooks-Atlanta, AUSTELL, GA, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
Hardcover. Condición: Very Good. No Jacket. May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less 1.4. Nº de ref. del artículo: G0792385586I4N00
Cantidad disponible: 1 disponibles
Imagen de archivo
Reuse Methodology Manual for System-on-a-Chip Designs
Librería: Better World Books: West, Reno, NV, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
Condición: Good. Used book that is in clean, average condition without any missing pages. Nº de ref. del artículo: 6387805-6
Cantidad disponible: 1 disponibles
Imagen del vendedor
Reuse Methodology Manual for System-on-a-Chip Designs
Librería: Goodwill of Silicon Valley, SAN JOSE, CA, Estados Unidos de America
Calificación del vendedor: 4 de 5 estrellas
Condición: acceptable. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Acceptable condition! Any other included accessories are also in Acceptable condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear such as cover tears discoloration, staining, marks, scuffs, etc. All pages intact. Nº de ref. del artículo: GWSVV.0792385586.A
Cantidad disponible: 1 disponibles
Imagen de archivo
Reuse Methodology Manual for System-on-a-Chip Designs
Librería: The Book Spot, Sioux Falls, MN, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
Hardcover. Condición: New. Nº de ref. del artículo: Abebooks250922
Cantidad disponible: 1 disponibles
Imagen de archivo
Reuse Methodology Manual for System-on-a-Chip Designs
Librería: Ria Christie Collections, Uxbridge, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Condición: New. In. Nº de ref. del artículo: ria9780792385585_new
Cantidad disponible: Más de 20 disponibles
Imagen de archivo
Reuse Methodology Manual for System-on-a-Chip Designs
Librería: HPB-Red, Dallas, TX, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
hardcover. Condición: Acceptable. Connecting readers with great books since 1972. Used textbooks may not include companion materials such as access codes, etc. May have condition issues including wear and notes/highlighting. We ship orders daily and Customer Service is our top priority! Nº de ref. del artículo: S_417283685
Cantidad disponible: 1 disponibles
Imagen de archivo
Reuse Methodology Manual for System-on-a-Chip Designs
Librería: HPB-Red, Dallas, TX, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
hardcover. Condición: Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority! Nº de ref. del artículo: S_430569160
Cantidad disponible: 1 disponibles
Imagen de archivo
Reuse Methodology Manual for System-on-a-Chip Designs
Publicado por
Kluwer Academic Publishers, 1999
ISBN 10: 0792385586
ISBN 13: 9780792385585
Nuevo
Tapa dura
Librería: THE SAINT BOOKSTORE, Southport, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Hardback. Condición: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 526. Nº de ref. del artículo: C9780792385585
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
Reuse Methodology Manual for System-On-A-Chip Designs
Librería: moluna, Greven, Alemania
Calificación del vendedor: 5 de 5 estrellas
Condición: New. Nº de ref. del artículo: 898701183
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
Reuse Methodology Manual for System-On-A-Chip Designs
Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Buch. Condición: Neu. Neuware - Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs. Nº de ref. del artículo: 9780792385585
Cantidad disponible: 2 disponibles