Introduction to Verilog Designer's Library: Developed by Bob Zeidman - Tapa blanda

Sinopsis

Hardware description languages (HDLs) use statements, like programming language statements, in order to define, simulate, synthesize and layout hardware. One of the main HDLs is Verilog, a widely used and standardized language. Verilog can be used to design anything from the most complex ASIC to the least complex PAL. As ASICs and FPGAs become more complex, HDLs become a necessity for their design. This course teachers how to use Verilog to design and simulate hardware. It begins by explaining the benefits of HDLs over other design entry methods, including its ability to model different levels of abstraction, its reusability and documentability. Next, the syntax of Verilog language is explained in detail. By the end of the course, you should be able to design and simulate real hardware using Verilog. The course includes: study guide, final exam, textbook ("Verilog Designer's Lirbary"), and one CD-ROM, eight CEUs and certificate of educational achievement upon successful completion.

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