Languages for precisely describing the behavior of computers have been studied since the conception of the computer itself. As the computer industry has grown, so has the need to exchange information about computers. Computer Hardware Description Languages (CHDL) are required to: - provide specifications and detailed implementation for a growing menu of sophisticated design automation tools, including synthesis, verification, simulation, analysis, optimization, placement, wiring and testing - communicate requirements and capabilities between suppliers and users of computer components and subsystems - facilitate the transfer of new methods and results within the university and industrial research community. As reflected in this book, there is an increased emphasis on applications and resulting requirements that are placed on CHDLs. In the field of synthesis , a major application area, there is today a focus on high-level synthesis and synthesis under design constraints. In the area of design correctness , research has shifted away from simulation to formal verification techniques such as temporal logic.
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Languages for precisely describing the behavior of computers have been studied since the conception of the computer itself. As the computer industry has grown, so has the need to exchange information about computers. Computer Hardware Description Languages (CHDL) are required to: - provide specifications and detailed implementation for a growing menu of sophisticated design automation tools, including synthesis, verification, simulation, analysis, optimization, placement, wiring and testing - communicate requirements and capabilities between suppliers and users of computer components and subsystems - facilitate the transfer of new methods and results within the university and industrial research community. As reflected in this book, there is an increased emphasis on applications and resulting requirements that are placed on CHDLs. In the field of synthesis , a major application area, there is today a focus on high-level synthesis and synthesis under design constraints. In the area of design correctness , research has shifted away from simulation to formal verification techniques such as temporal logic.
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