Systemverilog for Verification: A Guide to Learning the Testbench Language Features - Tapa dura

Spear, Chris

 
9780387270364: Systemverilog for Verification: A Guide to Learning the Testbench Language Features
Tapa dura
ISBN 10: 0387270361 ISBN 13: 9780387270364
Editorial: Springer-Verlag New York Inc., 2006

Sinopsis

"SystemVerilog for Verification" provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The authors explain methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types. For hardware engineers, the book has several chapters with detailed explanations of Object Oriented Programming based on years of teaching OOP to hundreds of students. For software engineers, there is a wealth of information on testbenches, multithreaded code, and interfacing to hardware designs. The reader only needs to know the Verilog 1995 standard.

"Sinopsis" puede pertenecer a otra edición de este libro.

Reseña del editor

SystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing. The book covers the SystemVerilog verification constructs such as classes, program blocks, C interface, randomization, and functional coverage. SystemVerilog for Verification also reviews some design topics such as interfaces and array types. There are extensive code examples and detailed explanations. The book will be based on Synopsys courses, seminars, and tutorials that the author developed for SystemVerilog, Vera, RVM, and OOP. Concepts will be built up chapter-by-chapter, and detailed testbench using these topics will be presented in the final chapter. SystemVerilog for Verification concentrates on the best practices for verifying your design using the power of the language.  

Reseña del editor

"SystemVerilog for Verification" provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The authors explain methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types. For hardware engineers, the book has several chapters with detailed explanations of Object Oriented Programming based on years of teaching OOP to hundreds of students. For software engineers, there is a wealth of information on testbenches, multithreaded code, and interfacing to hardware designs. The reader only needs to know the Verilog 1995 standard.

"Sobre este título" puede pertenecer a otra edición de este libro.

Editorial
Springer-Verlag New York Inc.
Año de publicación
2006
Idioma
Inglés
ISBN 10 
0387270361
ISBN 13 
9780387270364
Encuadernación
Tapa dura
Número de páginas
336
Contacto del fabricante
no disponible
Persona responsable
CMN Printpool Inh. Mathis Neumann
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