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Digital VLSI Chip Design with Cadence and Synopsys CAD Tools: VLSI CAD Lab Manual Ssp_4 - Tapa blanda
Sinopsis
Digital VLSI Chip Design with Cadence and Synopsys CAD Tools leads students through the complete process of building a ready-to-fabricate CMOS integrated circuit using popular commercial design software. Detailed tutorials include step-by-step instructions and screen shots of tool windows and dialog boxes. This hands-on book is for use in conjunction with a primary textbook on digital VLSI.
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Acerca del autor
Professor Erik Brunvand is an associate professor in the School of Computing at the University of Utah. He has interests in computer architecture and VLSI systems in general, and self-timed and asynchronous systems in particular. One aspect of his research involves compiling concurrent communicating programs into asynchronous VLSI circuits. The current system allows programs written in a subset of occam, a concurrent message-passing programming language based on CSP, to be automatically compiled into a set of self-timed circuit modules suitable for manufacture as an integrated circuit. He is also interested in investigating the effects of asynchrony on computer systems architecture at a higher level. To explore these ideas he is building a series of prototype asynchronous computer systems out of FPGA and custom VLSI chips.
De la contraportada
Digital VLSI Chip Design with Cadence and Synopsys CAD Tools leads students through the complete process of building a ready-to-fabricate CMOS integrated circuit using popular commercial design software. Detailed tutorials include step-by-step instructions and screen shots of tool windows and dialog boxes. This hands-on book is for use in conjunction with a primary textbook on digital VLSI.
University instructors may order Digital VLSI Chip Design with Cadence and Synopsys CAD Tools with the following textbooks:
[Rabaey Cover Image] Digital Integrated Circuits, 2nd Edition, by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikoli.
To order Digital Integrated Circuits, 2nd Edition packaged with Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, please use ISBN 0-13-509470-4 on your bookstore order form.
[Weste Cover Image] CMOS VLSI Design, 3rd Edition, by Neil H.E. Weste and David Harris.
To order CMOS VLSI Design, 3rd Edition packaged with Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, please use ISBN 0-13-509469-0 on your bookstore order form.
For further details, please contact your local Pearson (Addison-Wesley and Prentice Hall) sales representative or visit www.pearsonhighered.com.
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Digital VLSI Chip Design with Cadence and Synopsys CAD Tools
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Condición: New. Digital VLSI Chip Design with Cadence and Synopsys CAD Tools leads students through the complete process of building a ready-to-fabricate CMOS integrated circuit using popular commercial design software. Detailed tutorials include step-by-step instructions . Nº de ref. del artículo: 594526821
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Digital VLSI Chip Design with Cadence and Synopsys CAD Tools
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Pearson Education (US), 2009
ISBN 10: 0321547993
ISBN 13: 9780321547996
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Digital VLSI Chip Design with Cadence and Synopsys CAD Tools
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Taschenbuch. Condición: Neu. Neuware - Digital VLSI Chip Design with Cadence and Synopsys CAD Tools leads students through the complete process of building a ready-to-fabricate CMOS integrated circuit using popular commercial design software. Detailed tutorials include step-by-step instructions and screen shots of tool windows and dialog boxes. This hands-on book is for use in conjunction with a primary textbook on digital VLSI. Nº de ref. del artículo: 9780321547996
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