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Sinopsis
79434-7 It's About Time In today's high-speed designs, timing analysis is critical to success. This is the first book to focus exclusively on these crucial timing issues, with special emphasis on timing verification of ASICs. Timing Verification of Application Specific Integrated Circuits (ASICs) highlights principles and techniques over specific tools. This method makes the materials applicable to a variety of logic design approaches, especially in the field of deep submicron digital design. Topics include: * Clock definitions, multicycle paths, false paths, and phase-locked loops * Behavioral and structural RTL coding for timing * Timing analysis of FPGAs * Pre and Post layout timing analysis * Synthesis and Timing constraints * EDA timing tools Numerous design examples and Verilog codes offer practical illustrations of all the concepts. Timing Verification of Application Specific Integrated Circuits (ASICs) is a must for all logic designers concerned with the accuracy of timing and clock issues.
"Sinopsis" puede pertenecer a otra edición de este libro.
Acerca del autor
FARZAD NEKOOGAR, formerly a Technical Manager at Intrinsix Corp., has extensive practical experience verifying timing of ASICs, FPGAs, and systems-on-a-chip. He is a lecturer at the University of California at Davis, and is the author of "Digital Control Using Digital Signal Processing, " published by Prentice Hall PTR.
De la contraportada
79434-7
It's About Time
In today's high-speed designs, timing analysis is critical to success. This is the first book to focus exclusively on these crucial timing issues, with special emphasis on timing verification of ASICs. Timing Verification of Application Specific Integrated Circuits (ASICs) highlights principles and techniques over specific tools. This method makes the materials applicable to a variety of logic design approaches, especially in the field of deep submicron digital design. Topics include:
- Clock definitions, multicycle paths, false paths, and phase-locked loops
- Behavioral and structural RTL coding for timing
- Timing analysis of FPGAs
- Pre and Post layout timing analysis
- Synthesis and Timing constraints
- EDA timing tools
Numerous design examples and Verilog codes offer practical illustrations of all the concepts. Timing Verification of Application Specific Integrated Circuits (ASICs) is a must for all logic designers concerned with the accuracy of timing and clock issues.
"Sobre este título" puede pertenecer a otra edición de este libro.
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Timing Verification of Application-Specific Integrated Circuits
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Prentice Hall, 1999
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Timing Verification of Application-Specific Integrated Circuits
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Timing Verification of Application-Specific Integrated Circuits (ASICs)
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