Engineering the Complex SOC
The first unified hardware/software guide to processor-centric SOC design
Processor-centric approaches enable SOC designers to complete far larger projects in far less time. Engineering the Complex SOCis a comprehensive, example-driven guide to creating designs with configurable, extensible processors. Drawing upon Tensilica’s Xtensa architecture and TIE language, Dr. Chris Rowen systematically illuminates the issues, opportunities, and challenges of processor-centric design.
Rowen introduces a radically new design methodology, then covers its essential techniques: processor configuration, extension, hardware/software co-generation, multiple processor partitioning/communication, and more. Coverage includes:
Why extensible processors are necessary: shortcomings of current design methods
Comparing extensible processors to traditional processors and hardwired logic
Extensible processor architecture and mechanisms of processor extensibility
Latency, throughput, coordination of parallel functions, hardware interconnect options, management of design complexity, and other issues
Multiple-processor SOC architecture for embedded systems
Task design from the viewpoints of software andhardware developers
Advanced techniques: implementing complex state machines, task-to-task synchronization, power optimization, and more
Toward a “sea of processors”: Long-term trends in SOC design and semiconductor technology
For all architects, hardware engineers, software designers, and SOC program managers involved with complex SOC design; and for all managers investing in SOC designs, platforms, processors, or expertise.
PRENTICE HALL
Professional Technical Reference
Upper Saddle River, NJ 07458
www.phptr.com
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About the Author
DR. CHRIS ROWEN is President, CEO, and Founder of Tensilica, a leader in the automatic generation of application-specific microprocessors for high-volume systems. He pioneered RISC architecture at Stanford, helped start MIPS Computer Systems, and served as VP/General Manager of the Design Reuse Group at Synopsys. He holds a Ph.D. in electrical engineering from Stanford.
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