Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon) - Tapa dura

Acerca de los autores

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

Yao-Wen Chang, Ph.D., is a Professor in the Department of Electrical Engineering, National Taiwan University. He recevied his Ph.D. degree in Computer Science from the University of Texas at Austin. He has published over 200 technical papers, co-authored one book, and is a winner of the ACM ISPD Placement (2006) and Global Routing (2008) contests.

Kwang-Ting (Tim) Cheng, Ph.D., is a Professor and Chair of the Electrical and Computer Engineering Department at the University of California, Berkeley. A Fellow of the IEEE, he has published over 300 technical papers, co-authored three books, and holds 11 U.S. Patents.

De la contraportada

As semiconductor applications continue to advance and proliferate, the industry is increasingly dependent on design technologies for design closure and for meeting productivity goals. Electronic design automation (EDA), which has driven advances in design technologies for the past 30 years, will continue to play a critical role in the semiconductor food chain.

This book brings together a set of core EDA topics which provides an essential, fundamental understanding of the EDA tasks and the design process. Collectivley, these topics cover the core knowledge, software tools, algorithms, methodologies, and infrastructure required to optimize synthesis, verification, and manufacturing test of a functional and reliable integrated circuit.

The contents found within this book will enable the reader to understand fundamental EDA algorithms for synthesis and verification as well as very-large-scale intergartion (VLSI) test principles and DFT architectures to tackle EDA and test problems as advances in technology enter the nanometer era.