Artículos relacionados a Verification Techniques for System-Level Design (Systems...
Sinopsis
This book will explain how to verify SoC (Systems on Chip) logic designs using “formal” and “semiformal” verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in “functional” verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
"Sinopsis" puede pertenecer a otra edición de este libro.
Acerca de los autores
*Spent 15 years at Fujitsu research laboratories.
*Research on synthesis and verification of digital systems for more than 25 years
*Full professor at VLSI Design and Education Center in the University of Tokyo
Indradeep Ghosh received the Bachelor of Technology degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur, India, in 1993, and the M.A. and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, New Jersey, in 1995 and 1998, respectively.
Since 1998 he has been a member of research staff in at Fujitsu Laboratories of America, Sunnyvale, California. He has authored or co-authored more that 40 technical articles in international journals and conferences and holds 6 US patents. He has given numerous presentations in international conferences and workshops. In Fujitsu he has been involved in design verification and testing of industrial systems that are currently in production. His research interests include testing, verification, and validation of hardware and software systems. He is senior member of the IEEE and a member of the ACM.
Mukul Prasad:
Mukul Prasad received the Bachelor of Technology degree in Electrical Engineering from the Indian Institute of Technology, Delhi, India, in 1995, and the Ph.D. degree in Electrical Engineering & Computer Sciences from the University of California at Berkeley in 2001.
Since 2001 he has been a member of the research staff in the Trusted Systems Innovation group at Fujitsu Laboratories of America in Sunnyvale, California. His doctoral thesis and his subsequent research has involved the development and application of verification technologies such as Satisfiability solvers. His work has received a Best Paper Award at the Design Automation & Test in Europe Conference (DATE 2002). His current research addresses various problems in system-level design validation. He has co-authored more than 20 technical papers and presented three tutorials at international conferences and jointly holds 3 U.S. patents in the area of formal validation.
"Sobre este título" puede pertenecer a otra edición de este libro.
Comprar nuevo
Ver este artículo
EUR 62,90
EUR 11,00 gastos de envío desde Alemania a España
Destinos, gastos y plazos de envío
Resultados de la búsqueda para Verification Techniques for System-Level Design (Systems...
Imagen de archivo
Verification Techniques for System-Level Design
Publicado por
Elsevier, Amsterdam, 2008
ISBN 10: 0123706165
ISBN 13: 9780123706164
Antiguo o usado
Tapa dura
Librería: PsychoBabel & Skoob Books, Didcot, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
hardcover. Condición: Very Good. Estado de la sobrecubierta: No Dust Jacket. Name from previous owner on FEP. No dust jacket. Binding is very well preserved, pages are clean and crisp, and printing is tight, clean and bright throughout. MB. Used. Nº de ref. del artículo: 248182
Cantidad disponible: 1 disponibles
Imagen del vendedor
Verification Techniques for System-Level Design
Impresión bajo demandaLibrería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Calificación del vendedor: 5 de 5 estrellas
Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book will explain how to verify SoC (Systems on Chip) logic designs using 'formal? and 'semiformal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'functional? verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. . First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology. 256 pp. Englisch. Nº de ref. del artículo: 9780123706164
Cantidad disponible: 2 disponibles
Imagen del vendedor
Verification Techniques for System-Level Design
Impresión bajo demandaLibrería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Buch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book will explain how to verify SoC (Systems on Chip) logic designs using 'formal? and 'semiformal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'functional? verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. Nº de ref. del artículo: 9780123706164
Cantidad disponible: 2 disponibles
Imagen de archivo
Verification Techniques for System-Level Design (Systems on Silicon)
Publicado por
Morgan Kaufmann 2007-12-28, 2007
ISBN 10: 0123706165
ISBN 13: 9780123706164
Nuevo
Tapa dura
Librería: Chiron Media, Wallingford, Reino Unido
Calificación del vendedor: 4 de 5 estrellas
Hardcover. Condición: New. Nº de ref. del artículo: 6666-ELS-9780123706164
Cantidad disponible: Más de 20 disponibles
Imagen de archivo
Verification Techniques for System-level Design
Librería: Revaluation Books, Exeter, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Hardcover. Condición: Brand New. 1st edition. 256 pages. 9.50x7.50x1.00 inches. In Stock. Nº de ref. del artículo: __0123706165
Cantidad disponible: 2 disponibles
Imagen de archivo
Verification Techniques for System-Level Design
Librería: Majestic Books, Hounslow, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Condición: New. pp. viii + 240 Illus. Nº de ref. del artículo: 4212357
Cantidad disponible: 3 disponibles
Imagen de archivo
Verification Techniques for System-Level Design
Publicado por
Elsevier Science & Technology, 2007
ISBN 10: 0123706165
ISBN 13: 9780123706164
Nuevo
Tapa dura
Librería: THE SAINT BOOKSTORE, Southport, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Hardback. Condición: New. New copy - Usually dispatched within 4 working days. 697. Nº de ref. del artículo: B9780123706164
Cantidad disponible: Más de 20 disponibles
Imagen de archivo
Verification Techniques for System-Level Design
Librería: Books Puddle, New York, NY, Estados Unidos de America
Calificación del vendedor: 4 de 5 estrellas
Condición: New. pp. viii + 240. Nº de ref. del artículo: 263668314
Cantidad disponible: 3 disponibles
Imagen de archivo
Verification Techniques for System-Level Design
Librería: Biblios, Frankfurt am main, HESSE, Alemania
Calificación del vendedor: 5 de 5 estrellas
Condición: New. pp. viii + 240. Nº de ref. del artículo: 183668304
Cantidad disponible: 3 disponibles
Imagen de archivo
Verification Techniques for System-Level Design
Impresión bajo demandaLibrería: Brook Bookstore On Demand, Napoli, NA, Italia
Calificación del vendedor: 5 de 5 estrellas
Condición: new. Questo è un articolo print on demand. Nº de ref. del artículo: c42aaa410a91f5bf49b94a74b78c4b70
Cantidad disponible: Más de 20 disponibles