Multi-GHz Frequency Synthesis & Division: Frequency Synthesizer Design for 5 GHz Wireless LAN Systems - Tapa dura

In the past 10 years extensive effort has been dedicated to commercial wireless local area network (WLAN) systems. Despite all these efforts, however, none of the existing systems has been successful, mainly due to their low data rates. The increasing demand for WLAN systems that can support data rates in excess of 20 Mb/s enticed the FCC to create an unlicensed national information infrastructure (U–NII) band at 5 GHz. This frequency band provides 300 MHz of spectrum in two segments: a 200 MHz(5.15–5.35 GHz) and a 100 MHz (5.725–5.825 GHz) frequency band. This newly released spectrum, and the fast trend of CMOS scaling, provide an opportunity to design WLAN systems with high data rate and low cost. One of the existing standards at 5 GHz is the European high performance radio LAN (HIPERLAN) standard that supports data rates as high as 20 Mb/s. One of the main building blocks of each wireless system is the f- quency synthesizer. Phase–locked loops (PLLs) are universally used to design radio frequency synthesizers. Reducing the power consumption of the frequency dividers of a PLL has always been a challenge. In this book, we introduce an alternative solution for conventional flipflop based xiv MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION frequency dividers. An injection–locked frequency divider (ILFD) takes advantage of the narrowband nature of the wireless systems and employs resonators to trade off bandwidth for power.

There has been an increasing demand for Wireless Local Area Network (WLAN) systems in the past few years. New frequency bands are allocated and new standards are being developed to accommodate higher data rates. The fast trend of CMOS scaling has provided an opportunity for the development of low cost integrated WLAN systems.
Frequency synthesizers are one of the main building blocks of wireless transceivers. The high frequency digital frequency dividers in a phase-locked loop (PLL) based frequency synthesizer are among the most challenging blocks to design and usually account for a large percentage of the synthesizer total power dissipation. The successful design and integration of a high frequency PLL demands a comprehensive understanding of wireless systems, RF circuits, and loop stability issues.
Multi-GHz Frequency Synthesis & Division starts with an overview of WLAN systems and reviews the WLAN market and standards. It then studies PLLs as an essential building block of WLAN receivers, and provides guidelines and engineering recipes for the design of loop filters in high frequency PLLs. Additionally, the book investigates different analog and digital frequency division techniques and introduces injection-locked frequency dividers (ILFDs) as an alternative for conventional frequency dividers. Finally, the book demonstrates a successful design of a fully integrated CMOS frequency synthesizer for a 5 GHz WLAN receiver.
Multi-GHz Frequency Synthesis & Division will be of interest to RF and high-speed analog circuit designers and students as well as wireless engineers.