DFT+DFD: An Integrated Method for Design for Testability and Diagnosis: Enhancing Fault Coverage and Diagnostic Resolution Synergistically

 
9783843388016: DFT+DFD: An Integrated Method for Design for Testability and Diagnosis: Enhancing Fault Coverage and Diagnostic Resolution Synergistically

While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. This book targets test point insertions to detect more faults as well as to distinguish currently indistinguishable fault-pairs. This is achieved by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, a novel low-cost metric to identify such TD points is proposed. Further, a new DFT + DFD architecture is developed, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. In the other part, improving diagnosis in BIST environment is targeted. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories, response memory to store reference responses and fail memory to store failing responses. In this book, a novel architecture is proposed which requires only one additional memory and responses of only a small subset of available test patterns are stored.

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About the Author:

Nikhil Rahagude received the B.E. degree in Electronics Engineering from Veermata Jijabai Technological Institute, Mumbai, India in 2007 and the M.S. degree in Electrical and Computer Engineering from Virginia Tech, Blacksburg, USA in 2010. His interests include ATPG, fault diagnosis, design for testability (DFT) and design for diagnosis (DFD).

Nikhil Rahagude received the B.E. degree in Electronics Engineering from Veermata Jijabai Technological Institute, Mumbai, India in 2007 and the M.S. degree in Electrical and Computer Engineering from Virginia Tech, Blacksburg, USA in 2010. His interests include ATPG, fault diagnosis, design for testability (DFT) and design for diagnosis (DFD).

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Nikhil Rahagude
Editorial: LAP Lambert Academic Publishing 2011-02-17 (2011)
ISBN 10: 3843388016 ISBN 13: 9783843388016
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Descripción LAP Lambert Academic Publishing 2011-02-17, 2011. paperback. Estado de conservación: New. Nº de ref. de la librería 9783843388016

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Descripción Estado de conservación: New. Publisher/Verlag: LAP Lambert Academic Publishing | Enhancing Fault Coverage and Diagnostic Resolution Synergistically | While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. This book targets test point insertions to detect more faults as well as to distinguish currently indistinguishable fault-pairs. This is achieved by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, a novel low-cost metric to identify such TD points is proposed. Further, a new DFT + DFD architecture is developed, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. In the other part, improving diagnosis in BIST environment is targeted. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories, response memory to store reference responses and fail memory to store failing responses. In this book, a novel architecture is proposed which requires only one additional memory and responses of only a small subset of available test patterns are stored. | Format: Paperback | Language/Sprache: english | 144 gr | 96 pp. Nº de ref. de la librería K9783843388016

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Descripción LAP Lambert Acad. Publ. Feb 2011, 2011. Taschenbuch. Estado de conservación: Neu. This item is printed on demand - Print on Demand Neuware - While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. This book targets test point insertions to detect more faults as well as to distinguish currently indistinguishable fault-pairs. This is achieved by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, a novel low-cost metric to identify such TD points is proposed. Further, a new DFT + DFD architecture is developed, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. In the other part, improving diagnosis in BIST environment is targeted. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories, response memory to store reference responses and fail memory to store failing responses. In this book, a novel architecture is proposed which requires only one additional memory and responses of only a small subset of available test patterns are stored. 96 pp. Englisch. Nº de ref. de la librería 9783843388016

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Descripción LAP Lambert Acad. Publ. Feb 2011, 2011. Taschenbuch. Estado de conservación: Neu. Neuware - While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. This book targets test point insertions to detect more faults as well as to distinguish currently indistinguishable fault-pairs. This is achieved by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, a novel low-cost metric to identify such TD points is proposed. Further, a new DFT + DFD architecture is developed, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. In the other part, improving diagnosis in BIST environment is targeted. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories, response memory to store reference responses and fail memory to store failing responses. In this book, a novel architecture is proposed which requires only one additional memory and responses of only a small subset of available test patterns are stored. 96 pp. Englisch. Nº de ref. de la librería 9783843388016

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Nikhil Rahagude
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Descripción LAP Lambert Acad. Publ. Feb 2011, 2011. Taschenbuch. Estado de conservación: Neu. Neuware - While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. This book targets test point insertions to detect more faults as well as to distinguish currently indistinguishable fault-pairs. This is achieved by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, a novel low-cost metric to identify such TD points is proposed. Further, a new DFT + DFD architecture is developed, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. In the other part, improving diagnosis in BIST environment is targeted. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories, response memory to store reference responses and fail memory to store failing responses. In this book, a novel architecture is proposed which requires only one additional memory and responses of only a small subset of available test patterns are stored. 96 pp. Englisch. Nº de ref. de la librería 9783843388016

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Nikhil Rahagude
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Descripción LAP Lambert Academic Publishing, Germany, 2011. Paperback. Estado de conservación: New. Language: English . Brand New Book ***** Print on Demand *****.While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. This book targets test point insertions to detect more faults as well as to distinguish currently indistinguishable fault-pairs. This is achieved by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, a novel low-cost metric to identify such TD points is proposed. Further, a new DFT + DFD architecture is developed, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. In the other part, improving diagnosis in BIST environment is targeted. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories, response memory to store reference responses and fail memory to store failing responses. In this book, a novel architecture is proposed which requires only one additional memory and responses of only a small subset of available test patterns are stored. Nº de ref. de la librería AAV9783843388016

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