Computer Systems: Architectures, Modeling, and Simulation : Third and Fourth International Workshop, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings - Tapa blanda

Sinopsis

SAMOS III - Reconfigurable Computing.- The Molen Programming Paradigm.- Loading ??-Code: Design Considerations.- RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems.- Basic OS Support for Distributed Reconfigurable Hardware.- A Cost-Efficient RISC Processor Platform for Real Time Audio Applications.- Customising Processors: Design-Time and Run-Time Opportunities.- Intermediate Level Components for Reconfigurable Platforms.- Performance Estimation of Streaming Media Applications for Reconfigurable Platforms.- SAMOS III - Architectures and Implementation.- CoDeL: Automatically Synthesizing Network Interface Controllers.- Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units.- An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs.- Register-Based Permutation Networks for Stride Permutations.- A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures.- Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.- Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.- SAMOS III - Compilers, System Modeling, and Simulation.- Comparison of Data Dependence Analysis Tests.- MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code.- High-Level Energy Estimation for ARM-Based SOCs.- IDF Models for Trace Transformations: A Case Study in Computational Refinement.- Systems, Architectures, Modeling, and Simulation 2004 (SAMOS IV).- Programming Extremely Flexible Platforms.- SAMOS IV - Reconfigurable Computing.- The Virtex II ProTM MOLEN Processor.- Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements.- Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques.- Modeling Loop Unrolling: Approaches and Open Issues.- Self-loop Pipelining and Reconfigurable Dataflow Arrays.- Architecture Exploration for 3G Telephony Applications Using a Hardware-Software Prototyping Platform.- Embedded Context Aware Hardware Component Generation for Dataflow System Exploration.- On the (Re-)Use of IP-Components in Re-configurable Platforms.- Customising Hardware Designs for Elliptic Curve Cryptography.- Dynamic Hardware Reconfigurations: Performance Impact for MPEG2.- Compiler and System Techniques for soc Distributed Reconfigurable Accelerators.- SAMOS IV - Architectures and Implementation.- Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications.- On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering.- Memory Bandwidth Requirements of Tile-Based Rendering.- Using CoDeL to Rapidly Prototype Network Processsor Extensions.- Synchronous Transfer Architecture (STA).- Generated DSP Cores for Implementation of an OFDM Communication System.- A Novel Data-Path for Accelerating DSP Kernels.- Scalable FFT Processors and Pipelined Butterfly Units.- Scalable Instruction-Level Parallelism.- A Low-Power Multithreaded Processor for Baseband Communication Systems.- Initial Evaluation of Multimedia Extensions on VLIW Architectures.- HIBI v.2 Communication Network for System-on-Chip.- SAMOS IV - System Modeling, and Simulation.- DIF: An Interchange Format for Dataflow-Based Design Tools.- Scalable and Modular Scheduling.- Early ISS Integration into Network-on-Chip Designs.- Cycle Accurate Simulation Model Generation for SoC Prototyping.- Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.- A Communication-Centric Design Flow for HIBI-Based SoCs.- Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets.- Communication Optimization in Compaan Process Networks.- Analysis of Dataflow Programs with Interval-Limited Data-Rates.- High-Speed Event-Driven RTL Compiled Simulation.- A High-Level Programming Paradigm

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