Modeling and Simulation of ARM Processor Architecture: Using SystemC - Tapa blanda

Limachia, Mitesh; Kothari, Nikhil

 
9783659120886: Modeling and Simulation of ARM Processor Architecture: Using SystemC
Tapa blanda
ISBN 10: 365912088X ISBN 13: 9783659120886
Editorial: LAP LAMBERT Academic Publishing, 2012

Sinopsis

A software model of processor core created using HDL can serve as the master device to verify functionalities of various slave devices. The hard model available from the manufacture may not be flexible & compatible with the software platform for the verifications. This book presents ARM Cortex- M3 processor model generated with the help of a modeling and verification tool like SystemC having inbuilt functions to reduce coding complexity. ARM Cortex – M3 is a 32-bit RISC processor based on Thumb-2 core technology, which enhances performance with higher code densities. Increasing demand of high-end embedded applications such as mobile phones with space, power and cost constraints prefer RISC architecture against CISC. ARM architecture has made instructions simpler with fixed- length and easy pipelining in order to achieve single clock cycle throughput even at higher frequencies.

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Reseña del editor

A software model of processor core created using HDL can serve as the master device to verify functionalities of various slave devices. The hard model available from the manufacture may not be flexible & compatible with the software platform for the verifications. This book presents ARM Cortex- M3 processor model generated with the help of a modeling and verification tool like SystemC having inbuilt functions to reduce coding complexity. ARM Cortex - M3 is a 32-bit RISC processor based on Thumb-2 core technology, which enhances performance with higher code densities. Increasing demand of high-end embedded applications such as mobile phones with space, power and cost constraints prefer RISC architecture against CISC. ARM architecture has made instructions simpler with fixed- length and easy pipelining in order to achieve single clock cycle throughput even at higher frequencies.

Biografía del autor

Prof. Mitesh Limachia (Asst. Prof., Dept. of Electronics & Comm. Eng., D. D. University, Nadiad, India) received the M.E. degree from D. D. University, Nadiad. His areas of interest are low power VLSI designs and embedded systems. Dr. Nikhil Kothari (Professor & Head of Dept.) is working in the area of network protocols, besides embedded systems.

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Editorial
LAP LAMBERT Academic Publishing
Año de publicación
2012
Idioma
Inglés
ISBN 10 
365912088X
ISBN 13 
9783659120886
Encuadernación
Tapa blanda
Número de páginas
156
Contacto del fabricante
no disponible
Persona responsable
no disponible