Transaction-Level Power Modeling - Tapa blanda

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Amr Baher Darwish received his B.Sc and M.Sc degrees in Electronics Engineering from Ain Shams University, Cairo, Egypt, in 2011 and 2017, respectively. In 2011, he worked as Design Application Engineer for RF/AMS team, Intel Corporation, Cairo, Egypt. Between November 2013 and May 2016, he was Quality Assurance Engineer in IC Verification Solutions department at Mentor, a Siemens business, Cairo, Egypt. During June 2016 and April 2018, he worked as Backline Customer Support Engineer in the same company. Between October 2017 and March 2019, he worked as Senior Quality Assurance Engineer in Mentor. Currently, he is Questa SIM Product Engineer at Mentor, a Siemens business, Cairo, Egypt. Amr has published journal and conference papers in dynamic power estimation.

Magdy A. El-Moursy received the B.S. degree in electronics and communications engineering (with honors) and the Master's degree in computer networks from Cairo University, Cairo, Egypt, in 1996 and 2000, respectively, and the Master's and the Ph.D. degrees in electrical engineering in the area of high-performance VLSI/IC design from University of Rochester, Rochester, NY, USA, in 2002 and 2004, respectively. In summer of 2003, he was with STMicroelectronics, Advanced System Technology, San Diego, CA, USA. Between September 2004 and September 2006 he was a Senior Design Engineer at Portland Technology Development, Intel Corporation, Hillsboro, OR, USA. During September 2006 and February 2008 he was assistant professor in the Information Engineering and Technology Department of the German University in Cairo (GUC), Cairo, Egypt. Between February 2008 and October 2010 he was Technical Lead in the Mentor Hardware Emulation Division, Mentor Graphics Corporation, Cairo, Egypt.

Dr. El-Moursy is currently Engineering Manager in Integrated Circuits Verification Systems Division, Mentor, A Siemens Business and Associate Professor in the Microelectronics Department, Electronics Research Institute, Cairo, Egypt.  He is Associate Editor in the Editorial Board of Elsevier Microelectronics Journal, Journal of Circuits, Systems, and Computers, and International Journal of Circuits and Architecture Design and Technical Program Committee of many IEEE Conferences such as ISCAS, ICAINA, PacRim CCCSP, ISESD, SIECPC, and IDT. His research interest is in Networks-on-Chip/System-on-Chip, interconnect design and related circuit level issues in high performance VLSI circuits, clock distribution network design, digital ASIC circuit design, VLSI/SoC/NoC design and validation/verification, circuit verification and testing and low power design. He is the author of around 90 papers, six book chapters, and four books in the fields of high speed and low power CMOS design techniques and NoC/SoC.

Mohamed Dessouky received the B.Sc. and M.Sc. degrees in electrical engineering from the University of Ain Shams, Cairo, Egypt, in 1992 and 1995, respectively, and the Ph.D. degree in electrical engineering from the University of Paris VI, Paris, France, in 2001.  In 1992 he joined the Electronics and Electrical Communications Engineering Department, University of Ain Shams, where he is now a full Professor.  From 2010 to 2013 he was the director of the Integrated Circuits Lab at the same department. Prof. Dessouky was a visiting professor at the University of Paris VI in 2002 and 2004. From 2004 to 2010, he was on leave to Mentor Graphics Egypt, where he has been leading a mixed-signal design team responsible for the design of high-speed serial links. He also participated in the research and development of an EDA tool for technology porting of analog circuit designs. He is currently a staff Engineer at the same company. He also served in the Technical Committees of many IEEE Conferences such as DATE, SMACD, IDT and ICM. His research interests include custom digital design, ultra-low voltage design, analog-to-digital converters and CAD for analog and mixed-signal design.  Prof. Dessouky holds four US patents and has published several journal and conference papers in addition to a book chapter on analog layout design porting.

De la contraportada

This book describes for readers a methodology for dynamic power estimation, using Transaction Level Modeling (TLM). The methodology exploits the existing tools for RTL simulation, design synthesis and SystemC prototyping to provide fast and accurate power estimation using Transaction Level Power Modeling (TLPM).  Readers will benefit from this innovative way of evaluating power on a high level of abstraction, at an early stage of the product life cycle, decreasing the number of the expensive design iterations.