Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package (IEEE Press) - Tapa dura

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Beth Keser, PhD, is an IEEE Fellow and Distinguished Lecturer with over 23 years’ experience in the semiconductor industry and a co-Editor of Advances in Embedded and Fan-Out Wafer Level Packaging Technologies. Beth’s excellence in developing revolutionary electronic packages for semiconductor devices has resulted in 30 patents and patents pending and over 50 publications in the semiconductor industry.

Steffen Kröhnert is President & Founder of ESPAT-Consulting in Dresden, Germany. He is member of IEE EPS and co-Editor of Advances in Embedded and Fan-Out Wafer Level Packaging Technologies. Steffen has over 20 years’ experience in the semiconductor industry and is the author or co-author of 23 patent filings.

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Discover an up-to-date exploration of Embedded and Fan-Out Waver and Panel Level technologies

In Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package, a team of accomplished semiconductor experts delivers an in-depth treatment of various fan-out and embedded die approaches.

The book begins with a market analysis of the latest technology trends in Fan-Out and Wafer Level Packaging before moving on to a cost analysis of these solutions. The contributors discuss the new package types for advanced application spaces being created by companies like TSMC, Deca Technologies, and ASE Group. Finally, emerging technologies from academia are explored.

Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces is an indispensable resource for microelectronic package engineers, managers, and decision makers working with OEMs and IDMs. It is also a must-read for professors and graduate students working in microelectronics packaging research.