Artículos relacionados a VLSI Fault Modeling and Testing Techniques (Vlsi Design...
Sinopsis
VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.
"Sinopsis" puede pertenecer a otra edición de este libro.
Acerca del autor
brist /f George /i W.
"Sobre este título" puede pertenecer a otra edición de este libro.
EUR 19,76
EUR 64,21 gastos de envío desde Estados Unidos de America a España
Destinos, gastos y plazos de envíoComprar nuevo
Ver este artículo
EUR 77,94
EUR 17,11 gastos de envío desde Estados Unidos de America a España
Destinos, gastos y plazos de envíoResultados de la búsqueda para VLSI Fault Modeling and Testing Techniques (Vlsi Design...
Imagen de archivo
VLSI Fault Modeling and Testing Techniques: (VLSI Design Automation Series)
Librería: suffolkbooks, Center moriches, NY, Estados Unidos de America
Calificación del vendedor: 4 de 5 estrellas
hardcover. Condición: Very Good. Fast Shipping - Safe and Secure 7 days a week! Nº de ref. del artículo: 3TWDDA004QJM
Cantidad disponible: 2 disponibles
Imagen del vendedor
Vlsi Fault Modeling and Testing Techniques
Librería: GreatBookPrices, Columbia, MD, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
Condición: New. Nº de ref. del artículo: 823827-n
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
VLSI Fault Modeling and Testing Techniques
Publicado por
Ablex Publishing Corp., 1993
ISBN 10: 0893917818
ISBN 13: 9780893917814
Nuevo
Tapa dura
Librería: moluna, Greven, Alemania
Calificación del vendedor: 5 de 5 estrellas
Gebunden. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. This text explores VLSI fault modelling and testing techniques and covers such topics as: physical fault modelling and simulation for VSLI MOS circuits designing CMOS gates to test open faults testing bridging faults in VLSI and testable design synthesis. Nº de ref. del artículo: 447101356
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
Vlsi Fault Modeling and Testing Techniques
Librería: GreatBookPrices, Columbia, MD, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
Condición: As New. Unread book in perfect condition. Nº de ref. del artículo: 823827
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
VLSI Fault Modeling and Testing Techniques
Impresión bajo demandaLibrería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Buch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed. Nº de ref. del artículo: 9780893917814
Cantidad disponible: 1 disponibles
Imagen del vendedor
Vlsi Fault Modeling and Testing Techniques
Librería: GreatBookPricesUK, Woodford Green, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Condición: As New. Unread book in perfect condition. Nº de ref. del artículo: 823827
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
Vlsi Fault Modeling and Testing Techniques
Librería: GreatBookPricesUK, Woodford Green, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Condición: New. Nº de ref. del artículo: 823827-n
Cantidad disponible: Más de 20 disponibles
Imagen de archivo
Vlsi Fault Modeling and Testing Techniques
Librería: Revaluation Books, Exeter, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Hardcover. Condición: Brand New. 208 pages. 9.50x6.50x0.75 inches. In Stock. Nº de ref. del artículo: x-0893917818
Cantidad disponible: 2 disponibles
Imagen de archivo
VLSI Fault Modeling and Testing Techniques (Hardcover)
Publicado por
Bloomsbury Publishing Plc, Westport, 1993
ISBN 10: 0893917818
ISBN 13: 9780893917814
Nuevo
Tapa dura
Librería: CitiRetail, Stevenage, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Hardcover. Condición: new. Hardcover. VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed. This text explores VLSI fault modelling and testing techniques and covers such topics as: physical fault modelling and simulation for VSLI MOS circuits; designing CMOS gates to test open faults; testing bridging faults in VLSI; and testable design synthesis models. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability. Nº de ref. del artículo: 9780893917814
Cantidad disponible: 1 disponibles
Imagen del vendedor
VLSI Fault Modeling and Testing Techniques (Hardcover)
Publicado por
Bloomsbury Publishing Plc, Westport, 1993
ISBN 10: 0893917818
ISBN 13: 9780893917814
Nuevo
Tapa dura
Librería: Grand Eagle Retail, Mason, OH, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
Hardcover. Condición: new. Hardcover. VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed. This text explores VLSI fault modelling and testing techniques and covers such topics as: physical fault modelling and simulation for VSLI MOS circuits; designing CMOS gates to test open faults; testing bridging faults in VLSI; and testable design synthesis models. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Nº de ref. del artículo: 9780893917814
Cantidad disponible: 1 disponibles