Artículos relacionados a Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits:...
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits: 34 (Frontiers in Electronic Testing) - Tapa dura
Sinopsis
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
"Sinopsis" puede pertenecer a otra edición de este libro.
De la contraportada
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.
The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.
"Sobre este título" puede pertenecer a otra edición de este libro.
Comprar nuevo
Ver este artículo
EUR 174,70
EUR 9,88 gastos de envío desde Estados Unidos de America a España
Destinos, gastos y plazos de envíoOtras ediciones populares con el mismo título
Resultados de la búsqueda para Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits:...
Imagen de archivo
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Publicado por
Springer US, 2007
ISBN 10: 0387465464
ISBN 13: 9780387465463
Antiguo o usado
Tapa dura
Librería: Buchpark, Trebbin, Alemania
Calificación del vendedor: 5 de 5 estrellas
Condición: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher. Nº de ref. del artículo: 3284441/12
Cantidad disponible: 1 disponibles
Imagen del vendedor
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing, 34)
Librería: Solr Books, Lincolnwood, IL, Estados Unidos de America
Calificación del vendedor: 5 de 5 estrellas
Condición: very_good. This books is in Very good condition. There may be a few flaws like shelf wear and some light wear. Nº de ref. del artículo: BCV.0387465464.VG
Cantidad disponible: 1 disponibles
Imagen de archivo
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Librería: Books Puddle, New York, NY, Estados Unidos de America
Calificación del vendedor: 4 de 5 estrellas
Condición: New. pp. 352 2nd Edition. Nº de ref. del artículo: 26282698
Cantidad disponible: 1 disponibles
Imagen de archivo
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Librería: Majestic Books, Hounslow, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Condición: New. pp. 352 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam. Nº de ref. del artículo: 7597973
Cantidad disponible: 1 disponibles
Imagen del vendedor
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Impresión bajo demandaLibrería: moluna, Greven, Alemania
Calificación del vendedor: 5 de 5 estrellas
Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Wide coverage of topics in test engineeringUnique defect-oriented focus of the materialsIntroduction to yield engineering common practicesThe 2nd edition of defect oriented testing has been extensively updated. New cha. Nº de ref. del artículo: 5910370
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Impresión bajo demandaLibrería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Calificación del vendedor: 5 de 5 estrellas
Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance. 352 pp. Englisch. Nº de ref. del artículo: 9780387465463
Cantidad disponible: 2 disponibles
Imagen del vendedor
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Publicado por
Springer US, Springer New York, 2007
ISBN 10: 0387465464
ISBN 13: 9780387465463
Nuevo
Tapa dura
Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent. Nº de ref. del artículo: 9780387465463
Cantidad disponible: 1 disponibles
Imagen de archivo
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing, 34)
Librería: Ria Christie Collections, Uxbridge, Reino Unido
Calificación del vendedor: 5 de 5 estrellas
Condición: New. In. Nº de ref. del artículo: ria9780387465463_new
Cantidad disponible: Más de 20 disponibles
Imagen del vendedor
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Publicado por
Springer US, Springer New York Jun 2007, 2007
ISBN 10: 0387465464
ISBN 13: 9780387465463
Nuevo
Tapa dura
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
Calificación del vendedor: 5 de 5 estrellas
Buch. Condición: Neu. Neuware -Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 352 pp. Englisch. Nº de ref. del artículo: 9780387465463
Cantidad disponible: 2 disponibles
Imagen de archivo
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing (34))
Librería: Mispah books, Redhill, SURRE, Reino Unido
Calificación del vendedor: 4 de 5 estrellas
Hardcover. Condición: Like New. Like New. book. Nº de ref. del artículo: ERICA78703874654646
Cantidad disponible: 1 disponibles